Manufacture of wafer level semiconductor device with quality markings on the sealing resin

ABSTRACT

A method of manufacturing semiconductor device in the method of manufacturing wafer level semiconductor device that can search the defective products from the marking information even when sealing resin is formed on the wafer and a semiconductor device manufactured with the same method. A method of manufacturing wafer level semiconductor comprises a process to seal with a resin material the surface of wafer having the front surface and rear surface and forming a plurality of semiconductor chips on the front surface, a first marking process for marking the position information corresponding to each chip to the region of each chip at the rear surface of the wafer, a process for performing the electrical test to each chip, a second marking process for marking the result of the electrical test to the region of each chip at the rear surface of the wafer and a dicing process for dicing the wafer to each chip.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a division of Ser. No. 09/686,958, filed Oct.12, 2000, which is based on Japanese Application No. 2000-201416 filedJul. 3, 2000.

DETAILED DESCRIPTION OF THE INVENTION

[0002] Background of the Invention

[0003] The present invention relates to a method of manufacturing waferlevel semiconductor device and a semiconductor device wherein aplurality of chips and chip size packages (hereinafter referred to asCSP) are formed on the wafer and substrate.

[0004] There has been proposed a semiconductor package having thestructure that an external output terminal formed of a projectedelectrode is provided on a chip, in order to provide the shape ofsemiconductor package sealed with resin closely to a semiconductorelement (hereinafter referred to as chip) as much as possible, at leastthe side surface of projected electrode is sealed with resin under thewafer condition and thereafter each chip is diced. (Japanese PublishedUnexamined Patent Application No. HEI 10-79362; U.S. patent applicationSer. No. 09/029,608)

[0005] The present invention relates to a method for providingmanufacturing history used to conduct failure search of such wafer levelsemiconductor device and a semiconductor device manufactured using suchmethod.

[0006] Information including manufacturer name, type, manufacturing lotor the like has been marked on the resin of a semiconductor devicesurface in the semiconductor device of the type other than the waferlevel semiconductor device, namely the semiconductor package after thedicing and resin sealing. If a failure has occurred, history ofmanufacturing lot can be searched from this marking information andthereby cause of fault can be identified effectively.

[0007] The similar information is also marked in the wafer levelsemiconductor device of the related art.

[0008] In manufacture of semiconductor device using wafer includingwafer level semiconductor device, manufacturing processes are allperformed under the wafer condition but a fault is sometimes generatedfrom the particular position on the wafer. In this case, it is requiredto detect where a fault is generated on the wafer but since no markingis conducted on the chip in the manufacturing method of the related art,it is impossible to identify where a fault has occurred on the wafer.

[0009] Even if marking is conducted on the chip, it is required toexecute the process to melt the resin and it is considerably complicatedto confirm the marking after the sealing with resin.

BRIEF SUMMARY OF THE INVENTION

[0010] Therefore, it is an object of the present invention to provide amethod of manufacturing semiconductor device in the method ofmanufacturing wafer level semiconductor device where a fault can besearched from the marked information even after the sealing resin isformed on the wafer and a semiconductor device manufacturing with suchsemiconductor device manufacturing method.

[0011] The object of the invention is achieved by a method ofmanufacturing wafer level semiconductor device, comprising sealingprocess for sealing, with resin material, the front surface of a waferhaving the front and rear surfaces and having formed a plurality ofsemiconductor chips on the front surface, first marking process formarking the position information corresponding to each chip in theregion of each chip at the rear surface of the wafer, process forconducting electrical test to each chip, second marking process formarking the result of the electrical test corresponding to each chip inthe region of each chip at the rear surface of the wafer, and dicingprocess for dicing each chip.

[0012] Further, the object of the invention is achieved by a method ofmanufacturing wafer level semiconductor device comprising sealingprocess for sealing, with resin material, the front surface of a waferhaving the front and rear surfaces and having formed a plurality ofsemiconductor chips on the front surface thereof, process for conductingelectrical test to each chip, marking process for marking, in the regionof each chip at the rear surface of the wafer, the position informationcorresponding to each chip and the result of the electrical test, anddicing process for dicing each chip.

[0013] Further, the object of the invention is achieved by a method ofmanufacturing wafer level semiconductor device comprising sealingprocess for sealing, with resin material, the front surface of a waferhaving the front and rear surfaces and having formed a plurality ofsemiconductor chips on the front surface, attaching process forattaching, to the rear surface of wafer, a resin sheet on which markingis made on the wafer to indicate position of each chip and dicingprocess for dicing each chip.

[0014] Further, the object of the invention is achieved by asemiconductor device comprising a semiconductor chip diced from thepredetermined position of wafer wherein circuits are formed at the frontsurface, a resin sealing the front surface of the semiconductor chip, anexternal output terminal exposed from the resin and connected with thecircuits, and a marking provided at the rear surface of thesemiconductor chip to indicate the predetermined position of the wafer.

[0015] Further, the object of the invention is achieved by asemiconductor device comprising a semiconductor chip diced from thepredetermined position of a wafer where circuits are formed at the frontsurface, a resin for sealing the front surface of the semiconductorchip, an external output terminal exposed from the resin and connectedto the circuit, resin sheet attached to the rear surface of thesemiconductor chip and a marking for indicating the predeterminedposition of the wafer printed on the resin sheet.

[0016] Each means described above includes following operations.

[0017] According to the first manufacturing method described above,resin sealing and electrical test are performed under the wafercondition without dicing individual chips from the wafer and thereforewafer manufacturing record can easily be corresponding to the chipmanufacturing record. Moreover, marking can be made in the wafercondition before individual chips are diced into each chip. Therefore,when the manufacturing information is described at the time of marking,the chip manufacturing record is also left together with the positioninformation on the wafer of chip to individual chip after the dicing insuch a case that the manufacturing information is described at the timeof marking. Thereby, if a defective product is generated, the cause maybe searched easily and trace-ability can be improved.

[0018] According to the second manufacturing method described above,since the marking of position information can be executed in the sameprocess as the marking of the result of electrical test, effectivemarking may be realized by attempting twice the marking process asdescribed in the first method.

[0019] According to the third manufacturing method described above,since the resin sheet is used, the semiconductor package on which atleast position information is marked can be structured only by attachingthe resin sheet and the making can be done within a short period oftime.

[0020] According to the first semiconductor device as described above,the information suggesting where the chip in the semiconductor packageis located during the manufacturing process is marked and themanufacturing location record is left and therefore if a fault isgenerated, the cause of such fault may be searched easily and therebytrace-ability can be improved.

[0021] According to the second semiconductor device as described above,since the resin sheet is used in addition to the operation effectsimilar to that of the first device, the semiconductor package on whichthe position information is marked can be obtained at a low price.

BRIEF DESCRIPTION OF THE DRAWING

[0022] The object and advantages of the invention will become apparentand more readily appreciated from the following description of thepreferred embodiments, taken in conjunction with the accompanyingdrawing of which:

[0023]FIG. 1 is a diagram for explaining the manufacturing process ofthe first embodiment of the present invention.

[0024]FIG. 2 is a diagram for explaining the manufacturing process ofthe first embodiment of the present invention.

[0025]FIG. 3 is a diagram for explaining the manufacturing process ofthe first and second embodiments of the present invention.

[0026]FIG. 4 is a diagram for explaining the manufacturing process ofthe third embodiment of the present invention.

[0027]FIG. 5 is a diagram for explaining the manufacturing process ofthe fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Next, a preferred embodiment of the method of manufacturing waferlevel semiconductor device of the present invention will be explainedwith reference to FIG. 1 to FIG. 5.

[0029] The wafer level semiconductor device used in the presentinvention provides an external output terminal formed of a projectedelectrode composed of Cu or the like to the electrode on each chip ofwafer and is resin-sealed at its side surface of at least projectedelectrode under the wafer condition. Moreover, the wafer levelsemiconductor device of the present invention forms a plurality of chipat the surface thereof by the well known wafer process and those where aplurality of CSPs are formed on the substrate and these are resin-sealedat a time are also included in the wafer level semiconductor device.

[0030] (First Embodiment)

[0031] FIGS. 1(a) and 1(b) are diagrams for explaining the firstembodiment of the present invention indicating the resin sealing processof the wafer level semiconductor device of the first embodiment.

[0032] In these figures, numeral 1 designates a semiconductor waferwhere a plurality of CSPs or ordinary chips are formed. In more detail,this semiconductor wafer is disclosed in the Japanese PublishedUnexamined Patent Application No. HEI 10-79362.

[0033] On the chip or CSP formed on the wafer 1, pad electrodes areformed and the projected electrode (hereinafter called a post) is formedthereon as the external output terminal formed of copper or the like. Onthe circuit surface of wafer 1, the sealing resin is formed to protectthe chip formed on the wafer surface.

[0034] The sealing resin is formed in the following processes.

[0035] As illustrated in FIG. 1(a), the wafer 1 is placed in the cavityformed of an upper metal die 5 and a lower metal die 6. This cavity isformed a little larger than the wafer in size. The sealing resin isformed on the wafer by compression molding of the resin between theupper metal die 5 and lower metal die 6. But, a temporary film 4 isprovided in the upper metal die to easily separate the metal dies on theoccasion of taking the wafer from the metal dies.

[0036]FIG. 1(b) illustrates the process to form a sealing resin 3 to thewafer set in the metal dies of (a) through the compression mold ofresin.

[0037] In order to mold the sealing resin 3, a resin tablet (notillustrated) is placed first at the center of wafer, pressure is thenapplied to the upper and lower metal dies under application of heat, andthe resin tablet is widened on the wafer 1 to conduct the compressionmold. Thereby, the sealing resin 3 is formed covering the circuitsurface and side surface of the wafer. In place of the compression moldexplained above, the resin sealing can be realized also using theordinary transfer mold.

[0038] Next, the process to conduct marking, test and dicing to thewafer having completed the resin sealing will be explained withreference to FIGS. 2(a) to 2(d) and FIG. 3(a).

[0039]FIG. 2(a) illustrates the wafer under the condition havingcompleted the resin sealing explained above. The marking of positioninformation is performed in the process (b) to the region of each chipat the rear surface of chip for the rear surface 3 of the wafer in theopposite side of the circuit surface of this wafer to form the marking 2a. These processes correspond to the steps 41, 42 illustrated in FIG.3(a).

[0040] Position information indicates where the chip to be marked islocated on the wafer. For example, when the virtual X-Y axis is providedto the wafer and the numerals corresponding to such coordinates aremarked, the position information on the wafer can be indicated in eachchip.

[0041] In addition to the marking of the position information, the basicinformation including type of product, lot number and manufacturing weekcan also be marked here.

[0042] Moreover, this information can be marked based on the assemblinginformation stored in an assembling information storage memory 48 (FIG.3(a)) in regard to the fault generated at the time of resin sealing.This assembling information includes the position information indicatingwhere the partial fault of sealing resin generated at the time ofcompression mold is located on the wafer.

[0043] The mark 2 may be printed using the laser. The YAG laser or greenlaser is used and output of this laser is set to 300 to 500 mW.

[0044] Next, as illustrated in FIG. 3(c), electrical test is performedin the wafer level for each chip. Chip test is conducted by placing theprobe pin 12 in contact with the Cu post 10 as the external electrodeformed on each chip. The probe pin 12 may be placed in contact in unitof several pins and placed simultaneously with all pins of the chip.Moreover, the probe pin 12 maybe placed in contact with a plurality ofchips or the wafer contactor may be used for simultaneous contact to allwafers. These processes correspond to the step 43 illustrated in FIG.3(a).

[0045] Electrical test is performed to confirm whether the internalcircuit functions in correct or not for each chip and the burn-in testmay also be performed as required under the predetermined temperatureenvironment.

[0046] Result of this electrical test is stored in the test informationstorage memory 49. In this case, data of good product is stored togetherwith the position information to form the good product map data.

[0047] Thereafter, as illustrated (d), result of the electrical test ismarked in the region of each chip at the rear surface of the wafer toform the mark 2 b. This process corresponds to the step 44 illustratedin FIG. 3(a).

[0048] Result of this test may be performed to indicate good product ordefective product or to indicate only the good product. Moreover, thismarking may be performed for the good product in the predeterminedranks.

[0049] Finally, as illustrated in (d), dicing is conducted for each chipusing a dicing saw and as illustrated in (e), individual semiconductorpackage can be obtained. Only the good product of the semiconductorpackage are selected and delivered on the basis of the markedinformation explained above. These processes correspond to the steps 45,46, 47 illustrated in FIG. 3(a).

[0050] For this selection, the good product map data explained above isused and selection of only good product can be traced for confirmationby referring to the map data based on the position information withinthe wafer. Moreover, the defective product may be discriminated easilyby giving thereto the marking that-enables visual discrimination fromthe good product.

[0051] As explained above, since the resin sealing and electrical testare performed under the wafer condition without dicing of each chip fromthe wafer, the wafer manufacturing record may be easily set tocorrespond to the chip manufacture record. Moreover, according to thepresent embodiment, marking can be done under the wafer condition beforethe each chip can be isolated with the dicing process. Therefore, whenthe manufacturing information is described at the time of markingprocess, the chip manufacturing record is also left together with theposition information on the wafer of individual chip after the dicingprocess and thereby the cause may easily be traced if a fault isgenerated, thus improving the trace-ability in the failure search.

[0052] (Second Embodiment)

[0053]FIG. 3(b) is a diagram illustrating the second embodiment of thepresent invention.

[0054] Difference from FIG. 3(a) lies in that the marking of positioninformation is not performed before the electrical test 52 in the waferlevel but after this test.

[0055] As explained above, in this embodiment, since the marking of theposition information and marking of the result of electrical test areconducted in the same process, this marking can be realized moreeffectively than the two times of markings as illustrated in FIG. 3(a).

[0056] (Third Embodiment)

[0057]FIG. 4 is a diagram illustrating the third embodiment of thepresent invention.

[0058] This embodiment suggests the sealing of both surfaces of thewafer with the resin 3 a, 3 b as illustrated in FIG. 2.

[0059] As illustrated in (a), the circuit surface side is sealed withthe resin 3 a, while the opposite surface with the resin 3 b. Thissealing process can be conducted by conducting twice the methodexplained in FIG. 1 through upside down of the wafer.

[0060] Next, as illustrated in (b), the marking of position informationis performed to the resin 3 b in the opposite side of the circuitsurface as in the case of the first embodiment to form the mark 2.

[0061] Next, as illustrated in (c), the electrical test is performed, asin the case of the first embodiment, by placing the probe 12 in contactwith the Cu post 10 exposed from the resin 3 a at the circuit surface.

[0062] Finally, as illustrated in (d), the result of electrical test ismarked to the resin 3 b as in the case of the first embodiment. Theremaining processes may be performed in the same manner as the firstembodiment.

[0063] The marking process may be performed, as in the case of thesecond embodiment, by simultaneously marking both position informationand result of electrical test.

[0064] As explained above, marking can be performed to the resin surfacewith the existing facilities for printing the mark on the resin surfaceby sealing the both surfaces of wafer with resin and then printing themark on the resin surface.

[0065] (Fourth Embodiment)

[0066]FIG. 5 is a diagram for explaining the fourth embodiment of thepresent invention.

[0067] In this embodiment, the circuit surface and opposite surface ofthe wafer explained in FIG. 4 are formed of a resin sheet 7 ofheat-resistant organic material, for example, polyimide.

[0068] First, the circuit surface side is sealed with the resin 3 a.

[0069] Next, the position information is marked on the resin sheet 7 asin the case of the first embodiment.

[0070] Next, as in the case of the first embodiment, the electrical testis performed by placing the probe in contact with the Cu post exposedfrom the resin 3 a of the circuit surface and the result is marked onthe resin sheet 7. Thereafter, this resin sheet is attached to theopposite surface of the circuit surface of wafer. The remainingprocesses are performed in the same manner as the first embodiment forthe dicing of wafer to each chip.

[0071] The semiconductor package having the marking can be formed onlyby attaching the resin sheet through the use of such resin sheet and themarking can be performed only within a short period of time.

[0072] In the marking process, it is also possible, as in the case ofthe second embodiment, to simultaneously mark both position informationand result of electrical test on the resin sheet 7 and thereafter attachthe resin sheet having the marking to the rear surface of the wafer.

[0073] Thereby, the marking information including the positioninformation and result of electrical test is not required to temporarilyprint unlike the first embodiment and the result of electrical test canbe marked on the resin sheet simultaneously when the test is performed.

[0074] Moreover, it is also possible to previously print the numeralsand codes indicating the position information of the chip on the resinsheet and then attaching the resin sheet to the rear surface of waferunder the condition of FIG. 2(a). In this case, the result of electricaltest is not printed. The result of electrical test is no longer requiredto print on the resin sheet in the case where such result is stored inthe memory together with the position information of chip. Thereby, themarking process of the test result may be omitted and accordingly theprocesses may be saved.

[0075] [Effect of the Invention]

[0076] As explained above, according to the method of manufacturingwafer level semiconductor device of the present invention, since theinformation indicating where the internal chips are located on the wafercan be printed on the diced semiconductor package, the trace-ability ofsearch for defective product can be very much improved.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor chip diced from the predetermined position of waferwherein circuits are formed on the front surface, a resin sealing thefront surface of said semiconductor chip; an external output terminalexposed from said resin and connected with said circuits; and a markingprovided at the rear surface of said semiconductor chip to indicate thepredetermined position of said wafer.
 2. A semiconductor devicecomprising: a semiconductor chip diced from the predetermined positionof a wafer where circuits are formed on the front surface; a resinsealing the front surface of said semiconductor chip; an external outputterminal exposed from said resin and connected with said circuit; aresin sheet attached to the rear surface of said semiconductor chip; anda marking indicating the predetermined position of said wafer printed onsaid resin sheet.